2-4 Digital IC Learning

module HA(A, B, S, C);
	input A, B;
	output S, C;
	xor X_2(S, A, B); //实例化异或
	and A_2（C, A, B);
endmodule

module HA(A, B, S, C);
    input A, B;
    output S, C;
    wire W1, W2, W3;

    nand N_1(W1, A, B);
    nand N_2(W2, A, W1);
    nand N_3(W3, W1, B);
    nand N_4(S, W2, W3);
    nand N_5(C, W1, W1);
endmodule

module HA(A, B, S, C);
    input A, B;
    output S, C;
    wire W1, W2, W3;

    nor N_1(W1, A, A);
    nor N_2(W2, B, B);
    nor N_3(W3, A, B);
    nor N_4(C, W1, W2);
    nor N_5(S, W3, C);
endmodule

module FA(A, B, Cin, S, Co);
    input A, B, Cin;
    output S, Co;
    wire W1, W2, W3;

    xor X_1(S, A, B, Cin);
    and A_1(W1, A, B);
    and A_2(W2, A, Cin);
    and A_3(W3, B, Cin);
    or O_1(Co, W1, W2, W3);
endmodule

module FS(A, B, C, D, Bo);
    input A, B, C;
    output D, Bo;
    wire W1, W2, W3, W4;

    xor X_1(D, A, B, C);
    not n_1(W1, A);
    and A_1(W2, W1, C);
    and A_2(W3, W1, B);
    and A_3(W4, B, C);
    or O_1(Bo, W2, W3, W4);
endmodule

module mux_2x1(Y, I0, I1, S);
    input I0, I1, S;
    output Y;
    wire W1, W2, W3;

    not (W1, S);
    and (W2, I0, W1);
    and (W3, I1, S);
    or (Y, W2, W3);
endmodule

module mux_4x1(Y, I0, I1, I2, I3, S1, S0);
    input I0, I1, I2, I3, S1, S0;
    output Y;
    wire w1, w2, w3, w4, w5, w6;

    not (w1, S1);
    not (w2, S0);
    and (w3, I0, w1, w2);
    and (w4, I1, w1, S0);
    and (w5, I2, S1, w2);
    and (w6, I3, S1, S0);
    or (Y, w3, w4, w5, w6);
endmodule

module Dec_2to4(A, B, D0, D1, D2, D3);
    input A, B;
    output D0, D1, D2, D3;
    wire w1, w2;

    not (w1, A);
    not (w2, B);
    and (D0, w1, w2);
    and (D1, w1, B);
    and (D2, A, w2);
    and (D3, A, B);
endmodule

module Half_Add(X, Y, S, C);
    input X, Y;
    output S, C;

    assign S = X ^ Y;  // 异或操作，计算和
    assign C = X & Y;  // 与操作，计算进位

endmodule

module Half_Subtractor(X, Y, D, B);
    input X, Y;
    output D, B;

    assign D = X ^ Y;  // 异或操作，计算差值
    assign B = ~X & Y; // 与非操作，计算借位

endmodule

module mux_2x1_df(I0, I1, S, Y);
    input I0, I1, S;
    output Y;

    assign Y = (~S & I0) | (S & I1);
endmodule

module mux_4x1(y, i0, i1, i2, i3, s0, s1);
    input i0, i1, i2, i3, s0, s1;
    output y;

    assign y = (~s0 & ~s1 & i0) |
               (s0 & ~s1 & i1) |
               (~s0 & s1 & i2) |
               (s0 & s1 & i3);
endmodule

module ckt_tb();
    reg A, B, C;
    wire x, y;

    // 假设模块名称为Module_nameCKT，需要替换成实际使用的模块名
    Module_nameCKT inst (A, B, C, x, y);

    initial begin
        A = 1'b0; B = 1'b0; C = 1'b0;
        #100;
        A = 1'b1; B = 1'b1; C = 1'b1;
        #100 $stop;
    end
endmodule

// Testbench for Half adder
module HA_tb();
    reg A, B;
    wire S, C;

    // Instantiate the Half Adder module, assuming it is named Half_Add
    Half_Add Half (A, B, S, C);

    initial begin
        A = 0; B = 0;
        #5 A = 0; B = 1;
        #5 A = 1; B = 0;
        #5 A = 1; B = 1;
        #5 $stop;
    end
endmodule

module HS_tb();
	reg X, Y;
	wire D, B;
	Half_S Half(X, Y, D, B);
	initial
	begin
		X = 0; Y = 0;
		#5 X = 0; Y = 1;
		#5 X = 1; Y = 0;
		#5 X = 1; Y = 1;
		#5 $stop;
	end
endmodule 

// Testbench of 2 x 1 mux
module mux_tb();
    reg I0, I1, S;
    wire Y;

    // Instantiate the 2x1 multiplexer module, assuming its name is mux_2x1_df
    mux_2x1_df Mux(Y, I0, I1, S);

    initial begin
        // Test sequence
        I0 = 1'b1; I1 = 1'b0; // Set inputs
        #5 S = 1'b0;          // Set select to choose I0
        #5 S = 1'b1;          // Set select to choose I1
        #5 $stop;             // Stop simulation
    end
endmodule

// Testbench of 4 x 1 mux
module mux_tb();
    reg I0, I1, I2, I3, S1, S0;
    wire Y;

    // Instantiate the 4x1 multiplexer module
    mux_4x1 Mux(Y, I0, I1, I2, I3, S1, S0);

    initial begin
        // Initialize inputs
        I0 = 1; I1 = 0; I2 = 1; I3 = 0;
        #5 S1 = 0; S0 = 0;
        #5 S1 = 0; S0 = 1;
        #5 S1 = 1; S0 = 0;
        #5 S1 = 1; S0 = 1;
        #5 $finish; // End simulation
    end
endmodule

// Testbench of 2-to-4 Decoder
module Dec_tb();
    reg A, B;
    wire D0, D1, D2, D3;

    // Instantiate the 2-to-4 Decoder module, assuming it is named Dec_2to4
    Dec_2to4 Dec(A, B, D0, D1, D2, D3);

    initial begin
        A = 0; B = 0;
        #5 A = 0; B = 1;
        #5 A = 1; B = 0;
        #5 A = 1; B = 1;
        #5 $finish;
    end
endmodule

module half_adder(S, C, A, B);
    input A, B;
    output reg S, C;

    always @(A or B) begin
        if (A == 1 && B == 1) begin
            S = 0; C = 1;
        end else if (A == 1 || B == 1) begin
            S = 1; C = 0;
        end else begin
            S = 0; C = 0;
        end
    end
endmodule

module fulladder(S, C, x, y, z);
    input x, y, z;
    output S, C;
    wire S1, D1, D2;

    // Instantiate the half adders
    halfadder HA1(S1, D1, x, y);
    halfadder HA2(S, D2, S1, z);
    or g1(C, D2, D1);
endmodule

module bit_adder(S, C4, A, B, C0);
    input [3:0] A, B;
    input C0;
    output [3:0] S;
    output C4;
    wire C1, C2, C3;

    // Instantiate the full adder modules
    fulladder FA0(S[0], C1, A[0], B[0], C0),
              FA1(S[1], C2, A[1], B[1], C1),
              FA2(S[2], C3, A[2], B[2], C2),
              FA3(S[3], C4, A[3], B[3], C3);
endmodule

//if-else
module mux2x1_bh(A, B, select, OUT);
    input A, B, select;
    output reg OUT;

    always @(select or A or B) begin
        if (select == 1) 
            OUT = B;
        else 
            OUT = A;
    end
endmodule


//case
module mux2x1(A, B, select, out);
    input A, B;
    input select;
    output reg out;

    always @(A or B or select) begin
        case (select)
            1'b0: out = A;
            1'b1: out = B;
        endcase
    end
endmodule

// instantiate 3 2-1muxs into 1 4to1 mux
module Mux_4X1(S, I, Y);
    input [3:0] I;
    input [1:0] S;
    output reg Y;

    wire C1, C2;

    // Instantiate 2x1 multiplexers
    mux2x1_bh M0(I[0], I[1], S[0], C1),
              M1(I[2], I[3], S[0], C2),
              M2(C1, C2, S[1], Y);
endmodule

// case
module mux4x1(i0, i1, i2, i3, S, y);
    input i0, i1, i2, i3;
    input [1:0] S;
    output reg y;

    always @(i0 or i1 or i2 or i3 or S) begin
        case (S)
            2'b00: y = i0;
            2'b01: y = i1;
            2'b10: y = i2;
            2'b11: y = i3;
        endcase
    end
endmodule

// D-latch verilog
module d_latch(d, en, q);
    input d, en;
    output reg q;

    always @(en or d) begin
        if (en) begin
            q <= d;
        end
    end
endmodule

// D-latch testbench
module d_tb();
    reg d, en;
    wire q;
    
    // Instantiate the D-Latch
    d_latch D1(d, en, q);

    // Initial block for setting initial values and finishing the simulation
    initial begin
        en = 1'b0;
        d = 1'b1;
        #40 $finish;
    end

    // Toggle `en` every 5 time units
    always #5 en = ~en;

    // Toggle `d` every 7 time units
    always #7 d = ~d;
endmodule

// D-ff 
module d_ff(clk, d, rst, q);
    input clk, d, rst;
    output reg q;

    always @(posedge clk or negedge rst) begin
        if (!rst) begin
            q <= 1'b0;
        end else begin
            q <= d;
        end
    end
endmodule

// D-ff testbench
module d_tb();
    reg clk, d, rst;
    wire q;

    // Instantiate the D-FF
    d_ff D1(clk, d, rst, q);

    // Initialize signals and run the simulation
    initial begin
        clk = 1'b0; 
        rst = 1'b0; 
        d = 1'b0;
        #5 rst = 1'b1;
        #7 rst = 1'b0;
        #13 rst = 1'b1;
        #40 $finish;
    end

    // Toggle clock signal every 3 time units
    always #3 clk = ~clk;

    // Toggle data signal every 5 time units
    always #5 d = ~d;
endmodule

module JK (q, q1, j, k, clk);
    input j, k, clk;
    output reg q, q1;

    initial begin
        q = 1'b0;
        q1 = 1'b1;
    end

    always @(posedge clk) begin
        case ({j, k})
            2'b00: begin q = q; q1 = q1; end
            2'b01: begin q = 1'b0; q1 = 1'b1; end
            2'b10: begin q = 1'b1; q1 = 1'b0; end
            2'b11: begin q = ~q; q1 = ~q1; end
        endcase
    end
endmodule

// testbench
module JK_tb();
    reg clk, j, k;
    wire q, q1;

    // Instantiate the JK flip-flop
    JK J1(q, q1, j, k, clk);

    // Initialize signals and run the simulation
    initial begin
        clk = 1'b0; 
        j = 1'b1; 
        k = 1'b1;
        #25 $finish;
    end

    // Toggle clock signal every 2 time units
    always #2 clk = ~clk;
endmodule

module d_ff(clk, d, q, q_bar);
    input clk, d;
    output q, q_bar;
    reg q, q_bar;
    wire w1;

    // Inverting D to use as the K input for the JK flip-flop
    not N_1(w1, d);

    // Instantiating the JK flip-flop with the D input wired to J,
    // the inverted D wired to K, and the clock.
    // The Q and Q_bar outputs from the JK flip-flop will serve as the
    // D-type flip-flop's outputs.
    JK JK_d(q, q_bar, d, w1, clk);
endmodule

module T_ff(clk, T, q, q_bar);
    input clk, T;
    output q, q_bar;
    reg q;
    
    // q_bar is the inverse of q
    wire q_bar;
    assign q_bar = ~q;

    // Instantiate the JK flip-flop with both J and K inputs tied to T
    // When J and K are both high, the JK flip-flop toggles - which is the behavior of T flip-flop
    JK JK_d(q, q_bar, T, T, clk);
endmodule

module SR_ff(clk, S, R, q, q_bar);
    input clk, S, R;
    output reg q;
    output q_bar;

    // q_bar is the complement of q
    assign q_bar = ~q;

    // Instantiate the JK flip-flop
    // The J and K inputs are connected to the S and R inputs respectively.
    // Note that this JK instantiation assumes that the JK flip-flop has a 
    // built-in mechanism to handle the invalid state when J and K are both high.
    JK JK_SR(q, q_bar, S, R, clk);

    initial begin
        q = 1'b0;
        q_bar = 1'b1;
    end
endmodule

// NAND
module NAND_Switch(F, A, B);
    input A, B;
    output F;
    wire w1;
    
    supply1 Vdd;
    supply0 gnd;
    
    // PMOS switches connected to Vdd
    pmos P1(F, Vdd, A);
    pmos P2(F, Vdd, B);
    
    // NMOS switches connected in series with an intermediate node w1
    nmos N1(F, w1, A);
    nmos N2(w1, gnd, B);
endmodule

// Verilog Program for AND using switches
module AND_Switch(F, A, B);
    input A, B;
    output F;
    wire w1, F1;

    supply1 Vdd;
    supply0 gnd;

    // PMOS switches connected to Vdd for pull-up network
    pmos P1(F1, Vdd, A);
    pmos P2(F1, Vdd, B);

    // NMOS switches connected in series for pull-down network
    nmos N1(F1, w1, A);
    nmos N2(w1, gnd, B);

    // Output buffer to drive the signal F
    pmos P3(F, Vdd, F1);
    nmos N4(F, gnd, F1);
endmodule

// Nor
module switch_nor(out, a, b);
    output out;
    input a, b;

    // Internal wires
    wire w1;

    supply1 VDD; // Power (1) is connected to VDD
    supply0 GND; // Ground (0) is connected to GND

    // PMOS for pull-up network
    pmos (out, VDD, a); // When 'a' is LOW, connect 'out' to VDD
    pmos (out, VDD, b); // When 'b' is LOW, connect 'out' to VDD

    // NMOS for pull-down network
    nmos (out, w1, a); // When 'a' is HIGH, connect 'out' to 'w1'
    nmos (w1, GND, b); // When 'b' is HIGH, connect 'w1' to GND
endmodule

// 2x1 Multiplexer using CMOS switch
module mux2x1_switch(out, s, i0, i1);
    output out;
    input s, i0, i1;
    wire s1;

    // Instantiate the CMOS inverter
    snot U1(s1, s);

    // CMOS transmission gates for multiplexer functionality
    cmos (out, i0, s1, s);
    cmos (out, i1, s, s1);
endmodule

// CMOS inverter
module snot(s1, s);
    output sbar;
    input s;
    supply1 vdd;
    supply0 gnd;

    // CMOS inverter logic
    nmos (s1, gnd, s);
    pmos (s1, vdd, s);
endmodule

// 1-bit Full adder block using 4X1 multiplexer
module fulladder_Mux41_cmos(a, b, cin, sum, carry);
    input a, b, cin;
    output sum, carry;
    supply0 GND;
    supply1 Vdd;
    wire w1;

    not n1(w1, cin);
    mux41 x1(a, b, cin, w1, w1, cin, sum);
    mux41 x2(a, b, GND, cin, cin, Vdd, carry);
endmodule

// 4x1 Multiplexer block using switches.
module mux41(s0, s1, i0, i1, i2, i3, y);
    input s0, s1, i0, i1, i2, i3;
    output y;
    supply0 GND;
    supply1 Vdd;
    wire w1, w2, w3, w4;

    nmos n1(w1, Vdd, s0);
    pmos p1(w1, GND, s0);
    nmos n2(w2, Vdd, s1);
    pmos p2(w2, GND, s1);
    cmos c1(w3, i0, s0, w1);
    cmos c2(w3, i1, w1, s0);
    cmos c3(w4, i2, s0, w1);
    cmos c4(w4, i3, w1, s0);
    cmos c5(y, w3, s1, w2);
    cmos c6(y, w4, w2, s1);
endmodule

// Verilog test stimulus for 1-bit Full adder
module fulladder_cmos_test;
    reg a, b, cin;
    wire sum, carry;

    fulladder_Mux41_cmos f1(a, b, cin, sum, carry);

    initial begin
        a = 0; b = 0; cin = 0;
        #3 a = 0; b = 0; cin = 1;
        #3 a = 0; b = 1; cin = 0;
        #3 a = 0; b = 1; cin = 1;
        #3 a = 1; b = 0; cin = 0;
        #3 a = 1; b = 0; cin = 1;
        #3 a = 1; b = 1; cin = 0;
        #3 a = 1; b = 1; cin = 1;
        #3 $stop;
    end
endmodule

// Program P8.1
module distributed_delay (F, A, B, C, D);
    output F;
    input A, B, C, D;
    wire w1, w2;

    or #3 x1(w1, A, B);
    or #3 x2(w2, C, D);
    and #2 x3(F, w1, w2);
endmodule

// Program P8.2
module distributed_delay (F, A, B, C, D);
    output F;
    input A, B, C, D;
    wire w1, w2;

    assign #3 w1 = A & B;
    assign #3 w2 = C & D;
    assign #2 F = w1 & w2;
endmodule

// Program P8.3
module lumped_delay (F, A, B, C, D);
    output F;
    input A, B, C, D;
    wire w1, w2;

    assign w1 = A & B;
    assign w2 = C & D;
    assign #5 F = w1 & w2;
endmodule

// Program P8.4
module path_delay (F, A, B, C, D);
    output F;
    input A, B, C, D;
    wire w1, w2;

    specify
        (A => F) = 5;
        (B => F) = 6;
        (C => F) = 7;
        (D => F) = 8;
    endspecify

    assign w1 = A & B;
    assign w2 = C & D;
    assign #5 F = w1 & w2;
endmodule

// 格式
primitive name_of_UDP (output, input1, input2);
    // Declaration of ports
    output reg output; // optional

    // Initial block to set an initial value for the output
    initial begin
        output = some_initial_value; // optional
    end

    // Truth table defining the behavior of the UDP
    table
        // truth table
    endtable
endprimitive

// Program P8.6
primitive my_and (f, a, b);
    output f;
    input a, b;

    table
    // a b : f
        0 0 : 0;
        0 1 : 0;
        1 0 : 0;
        1 1 : 1;
    endtable
endprimitive

// Program P8.10
primitive dff (q, d, clock, rst);
    output q;
    input d, clock, rst;
    reg q;

    initial begin
        q = 0; // Set initial value of q
    end

    table
        // d  clock  rst : current q : next q
        ?   ?      1   : ?         : 0;  // reset condition
        0   1      0   : ?         : 0;  // clk level high, store 0
        1   1      0   : ?         : 1;  // clk level high, store 1
        ?   0      ?   : ?         : -;  // clk level low, no change
    endtable
endprimitive

// Primitive definition for an edge-triggered D flip-flop
primitive EDff (q, d, clk, rst);
    output q;    // Output of the flip-flop
    input d, clk, rst;  // Data, clock, and reset inputs
    reg q;       // Internal storage for the output

    // Set initial value of q
    initial q = 0;

    // Define the behavior of the flip-flop with a truth table
    table
        // d clk rst : current q : next q
        ?  ?  1   :  ?   : 0;  // Reset condition
        ? (0?) 0   :  ?   : -;  // Ignore positive edge of the clock
        ? (x1) 0   :  ?   : -;  // Ignore unknown positive edge of the clock
        ? (1x) 0   :  ?   : -;  // Ignore unknown negative edge of the clock
        1 (10) 0   :  ?   : 1;  // Output follows d at negative edge of the clock
        0 (10) 0   :  ?   : 0;  // Output follows d at negative edge of the clock
        (??) 0 0   :  ?   : -;  // No change on d when clk is stable
    endtable
endprimitive

// Program P8.16
module operation(ab_and, ab_or, ab_xor, a, b);
    input [15:0] a, b;
    output [15:0] ab_and, ab_or, ab_xor;
    reg [15:0] ab_and, ab_or, ab_xor;

    always @(a or b) begin
        bitwise_oper(ab_and, ab_or, ab_xor, a, b); // Task Invocation
    end

    task bitwise_oper;
        output [15:0] ab_and, ab_or, ab_xor;
        input [15:0] a, b;
        begin
            ab_and = a & b;
            ab_or = a | b;
            ab_xor = a ^ b;
        end
    endtask
endmodule

// Program P8.17
module parity(parity, address);
    input [31:0] address;
    output parity;
    reg parity;

    always @(address) begin
        parity = check_parity(address); // function invocation
        $display("Parity calculated = %b", parity); // function invocation
    end

    function check_parity;
        input [31:0] addr;
        begin
            // Calculate parity by XOR'ing all bits of the address
            check_parity = ^addr;
        end
    endfunction
endmodule

### 设计规格 (Design Specifications)
设计者根据功耗、面积延迟等标准和要求被提供特定的设计规格。

### 设计分区 (Design Partitioning)
设计师被允许执行设计分区，以增强灵活性和简化设计。

### 设计输入 (Design Entry)
这用于将设计输入到一个ASIC设计系统中，可以通过硬件描述语言（HDL）或原理图输入来完成。

### 功能验证 (Functional Verification)
在这一步中，电路设计被验证，即，系统功能是否按照预期规格运行。如果不是，则在这里更改设计输入。静态时序分析、FPGA上的批处理流程（制造）功能验证规范系统分区（对于大型系统）设计输入功能验证逻辑综合楼层规划放置及设计师的路由回注。

### FPGA上的原型制作 (Prototyping on FPGA)
当后布局仿真正确完成后，可以通过在FPGA上烧录软件代码来设计原型。

### 制造 (Manufacturing)
在设计出原型后，将根据设计的原型制造芯片。

// Main module
module Switch_fulladd(S, C, u, v, w); // Top module and port declaration
    input u, v, w;
    output S, C;

    wire y1, c1, c2;

    sxor u1(y1, u, v);
    sxor u2(S, y1, w);
    sand u3(c1, u, v);
    sand u4(c2, y1, w);
    sor u5(C, c2, c1);
endmodule

// Module for OR gate using switches (sor)
module sor(f, x, y); // Module elaboration of OR-gate using switch (sor)
    input x, y;
    output f;
    wire w;

    snor x1(w, x, y); // Call of module switch NOR-gate
    snot x2(f, w);
endmodule

module snor (Op, x, y);
  output Op;
  input x, y;
  wire w;
  supply1 Vdd;
  supply0 Gnd;
  
  pmos (w, Vdd, y);
  pmos (Op, w, x);
  nmos (Op, Gnd, x);
  nmos (Op, Gnd, y);
endmodule

module sxor (Op, x, y);
  input x, y;
  output Op;
  wire w1, w2, w3, w4, w5;
  supply1 Vdd;
  supply0 Gnd;
  
  nmos (w3, Gnd, w2);
  nmos (Op, w3, w1);
  nmos (w4, Gnd, y);
  nmos (Op, w4, x);
  pmos (Op, w5, x);
  pmos (Op, w5, y);
  pmos (w5, Vdd, w1);
  pmos (w5, Vdd, w2);
  snot nl (w1, x);
  snot n2 (w2, y);
endmodule

module sand (Op, x, y);
  output Op;
  input x, y;
  wire w;
  snand x1 (w, x, y);
  snot x2 (Op, w);
endmodule

module snand (Op, x, y);
  output Op;
  input x, y;
  wire c;
  supply1 Vdd;
  supply0 Gnd;
  
  pmos (Op, Vdd, y);
  pmos (Op, Vdd, x);
  nmos (w, Gnd, x);
  nmos (Op, w, y);
endmodule

module snot (Op, x);
  input x;
  output Op;
  supply1 Vdd;
  supply0 Gnd;
  
  nmos (Op, Gnd, x);
  pmos (Op, Vdd, x);
endmodule

module RCFA_4_bit (M, Cout, U, V, Cin);
    input [3:0] U, V;
    input Cin;
    output [3:0] M;
    output Cout;
    wire C0, C1, C2;
    // 串联即可
    fulladd f1(M[0], C0, U[0], V[0], Cin);
    fulladd f2(M[1], C1, U[1], V[1], C0);
    fulladd f3(M[2], C2, U[2], V[2], C1);
    fulladd f4(M[3], Cout, U[3], V[3], C2);
endmodule

// Design module
module carrylookahead_adder(S, Cout, U, V, Cin);

    input [3:0] U, V;
    input Cin;
    output [3:0] S;
    output Cout;

    wire h0, k0, h1, k1, h2, k2, h3, k3;
    wire C3, C2, C1;

    assign k0 = U[0] ^ V[0];
    assign k1 = U[1] ^ V[1];
    assign k2 = U[2] ^ V[2];
    assign k3 = U[3] ^ V[3];

    assign h0 = U[0] & V[0];
    assign h1 = U[1] & V[1];
    assign h2 = U[2] & V[2];
    assign h3 = U[3] & V[3];

    assign S[0] = U[0] ^ V[0] ^ Cin;
    assign S[1] = U[1] ^ V[1] ^ C1;
    assign S[2] = U[2] ^ V[2] ^ C2;
    assign S[3] = U[3] ^ V[3] ^ C3;

    assign C1 = h0 & (k0 & Cin);
    assign C2 = h1 & (k1 & C1);
    assign C3 = h2 & (k2 & C2);
    assign Cout = h3 & (k3 & C3);

endmodule

// Test Stimulus
module carrylookahead_adder_test;

    reg [3:0] U, V;
    reg Cin;
    wire [3:0] S;
    wire Cout;

    carrylookahead_adder u(S, Cout, U, V, Cin);

    initial begin
        $monitor($time, "S = %d, Cout = %d, U = %b, V = %b, Cin = %b", S, Cout, U, V, Cin);
        U = 4'd1; V = 4'd2; Cin = 0;
        #15 U = 4'd2; V = 4'd5; Cin = 0;
        #15 U = 4'd4; V = 4'd4; Cin = 1;
        #15 U = 4'd3; V = 4'd5; Cin = 0;
        #20 $stop;
    end

endmodule

// Main module
module CSA(u, v, w, s, cout);
    input [3:0] u, v, w;
    output [4:0] s;
    output cout;
    wire [3:0] c1, s1, c2;

    fulladd fa_10(u[0], v[0], w[0], s1[0], c1[0]); // calling of full blocks
    fulladd fa_11(u[1], v[1], w[1], s1[1], c1[1]);
    fulladd fa_12(u[2], v[2], w[2], s1[2], c1[2]);
    fulladd fa_13(u[3], v[3], w[3], s1[3], c1[3]);
    fulladd fa_20(s1[1], c1[0], 1'b0, s[1], c2[1]);
    fulladd fa_21(s1[2], c1[1], c2[1], s[2], c2[2]);
    fulladd fa_22(s1[3], c1[2], c2[2], s[3], c2[3]);
    fulladd fa_23(1'b0, c1[3], c2[3], s[4], cout);
    assign s[0] = s1[0];
endmodule

module arraymultiplier_2bit(C, X, Y);
    input [1:0] X, Y;
    output [3:0] C;
    wire w1, w2, w3, w4;
    and x1(C[0], X[0], Y[0]);
    and x2(w1, X[0], Y[1]);
    and x3(w2, X[1], Y[0]);
    and x4(w4, X[1], Y[1]);
    ha h1(C[1], w3, w1, w2);
    ha h2(C[2], C[3], w3, w4);
endmodule

module ha(s, c, x, y);
    input x, y;
    output s, c;
    xor r1(s, x, y);
    and r2(c, x, y);
endmodule

module arraymultiplier_2bit_test;
    reg [1:0] x, y;
    wire [3:0] C;
    arraymultiplier_2bit u(C, x, y);
    initial begin
        x = 2'd0; y = 2'd0;
        #5 x = 2'd0; y = 2'd1;
        #5 x = 2'd1; y = 2'd0;
        #5 x = 2'd2; y = 2'd3;
        #5 $stop;
    end
endmodule